The RFIC / mmWave Designer Almost Nobody in the US Staffs

You need someone to own the mmWave front-end on a 5G module or a SATCOM phased array. The PA and LNA blocks have to hit spec, tape out, and characterize on schedule. You post the req, and the US search returns RAN engineers who deploy base stations, network staffers who recruit for telecom rollouts, and a handful of UK firms that actually place RFIC designers. Six months later the seat is still open, because the people who can design a silicon-proven mmWave front-end in the United States are a very small pool, and most staffing firms do not know what to screen for.

RFIC and mmWave design is transistor-level analog physics. It is measured in decibels and dBm, not lines of code, and the signal that matters on a résumé is not “RF experience.” It is silicon-proven: a block this engineer designed that came back from the foundry and met its specs on the bench. This is how to find that person, and why they are so hard to source.

What an RFIC / mmWave Designer Really Owns

These are analog designers who think at the transistor level, closer to physicists than to software engineers. They own the radio building blocks: the LNA where noise figure is everything, the mixer, the VCO and PLL where phase noise decides the link, and the PA where linearity, P1dB, efficiency, and thermal all fight each other. At mmWave the job expands to beamforming ICs and phased-array front-ends, where dozens of elements have to stay aligned in phase and amplitude.

They live by RF metrics: noise figure, IP3, P1dB, and EVM. They make process-selection calls that a generalist would not know exist, choosing between CMOS RF, SiGe, GaAs, and GaN based on frequency, linearity, power, and integration tradeoffs. And at mmWave bands like 28 GHz and 39 GHz for 5G, layout becomes part of the circuit: parasitics, electromagnetic coupling, and in-package antennas mean the physical design and the schematic cannot be separated. The toolset reflects all of this, built around Cadence Virtuoso, SpectreRF, and Keysight ADS, and bound tightly to a foundry PDK. None of that shows up when a search screens for the word “wireless.”

Why US Teams Struggle to Source This Talent, and Why UK Firms Own the SERP

The pool is genuinely thin. RFIC is a narrow slice of analog design, mmWave narrows it further, and silicon-proven experience at RF nodes narrows it again. Analog talent is already among the scarcest in the industry, and RF is one of its thinnest layers. Deloitte projects a global semiconductor workforce shortage of more than a million people by 2030, and the analog and RF specialties feel it more acutely than most, because the skill takes years of taped-out silicon to build.

Demand is climbing from three directions at once. 5G mmWave infrastructure and handsets need it, defense phased-array radar and electronic warfare need it, and the LEO satellite build-out is adding electronically steerable antennas at scale (Qorvo). The same few hundred designers are being courted by all three at the same time.

Then there is the search problem. Look up “hire RFIC engineer” or “mmWave designer staffing” in the US and the results are dominated by UK specialist firms and by telecom staffers recruiting RAN and network engineers. RAN and RFIC are different worlds. The engineer who deploys and optimizes a base station is not the engineer who designs the power amplifier inside it. US teams end up served by whoever ranks, which is rarely a firm that screens for measured silicon. That gap, not a lack of open roles, is what leaves these seats empty.

Silicon-Proven vs. Simulation-Only: How to Tell in a Screen

This is the single most important distinction, and it is easy to miss. A simulation-only designer can drive SpectreRF and ADS and produce clean, confident simulations. A silicon-proven designer has taped out, gotten parts back, and measured noise figure, IP3, P1dB, and EVM on the bench, then closed the gap between what the simulator promised and what the silicon actually did. At mmWave that gap is brutal, because parasitics, packaging, and process variation punish anyone who trusted simulation alone.

Screen for the measurement, not the simulation. A few questions that separate the two quickly:

• “Tell me about a block where measured silicon diverged from your simulation. What caused it, and what did you change?” A silicon-proven designer has this story ready. A simulation-only candidate does not.
• “Walk me through your de-embedding and on-wafer probing setup on your last RF characterization.” Bench and characterization detail is hard to fake.
• “Which process did you choose for that PA, and why that one over the alternatives?” Listen for a real CMOS-vs-SiGe-vs-GaN tradeoff tied to frequency, linearity, and thermal.
• “How did you hit your phase and amplitude matching across a phased-array front-end?” For mmWave roles, this surfaces genuine array experience versus single-block work.
  

Where RFIC / mmWave Fits on a Wireless SoC or Module Schedule

RF blocks are long-lead and sit squarely on the critical path. Analog and RF design and layout are slow by nature, tape-out is a hard gate, and characterization only happens once parts come back from the foundry. A late RF front-end does not slip quietly; it drags the whole module with it, because the front-end often sets system-level performance through the link budget and receiver sensitivity.

That means the RF owner has to be in place early, during architecture and block design, not brought in to firefight after a spec miss. It also means the same person, or someone equally silicon-proven, needs to be there at bring-up and characterization months later. Under-owning this block is one of the more expensive mistakes a wireless program can make, and it is the hardest to recover from late.

Contract vs. FTE for a Narrow, Deadline-Bound RF Block

RF demand pulses harder than almost any other discipline. It is intense during block design and again at characterization, and quiet in the stretches between tape-outs. Carrying a principal mmWave designer as permanent headcount across those quiet stretches is expensive idle capacity for a skill this specialized.

Contract fits the shape of the work: a specific block such as a PA, LNA, VCO, or beamformer to design and characterize against a deadline, or a gap to cover when your one RF designer leaves mid-program. Contract RFIC designers who have taped out across multiple companies bring measured-silicon experience across processes and frequency bands, which is exactly the judgment a simulation-only hire lacks. Keep the work full-time where RF is your core product and needs multi-year ownership.

For context on the search itself: RFIC and mmWave design is one of the scarcest analog specialties in the US, and the talent shortage is not easing. Game 7 staffs US RFIC and mmWave designers specifically, adjacent to the Qualcomm, NXP, and Broadcom base we already serve. Our median fill for principal-level chip, board, and embedded engineers is 31 days, against a 58-day industry average for engineering roles that runs past 100 for niche disciplines, and our 2025–26 interview-to-offer ratio is 1.46:1, so your RF leads are not spending their scarce bench time screening the wrong candidates.