SerDes Design
High-Speed SerDes Designers, 28G Through 112G PAM4
SerDes is the circulatory system of modern semiconductor. Engineers with silicon-proven 112G PAM4 at 7nm or 5nm are among the most valuable in the industry. And we staff them.
What they do
From Transistor Sizing Through BER Correlation
SerDes engineers at Game 7 design the analog front end, clock recovery, transmitter drivers, and DSP adaptation algorithms that move data at 56G, 112G, or 224G PAM4. They understand link budget. The sum of insertion loss, return loss, crosstalk, and jitter that determines whether the link closes BER at the system level.
They co-design with the PCB SI team, run IBIS-AMI analysis on real channels, and correlate silicon measurements to pre-silicon simulation.
Scope of work
- Analog front-end design: CTLE, DFE, CDR, and decision feedback circuits for Rx path
- Transmit driver design: pre-emphasis, de-emphasis, and output swing calibration
- PLL and clock recovery circuit design to jitter performance targets
- PAM4 signal processing: DSP algorithm design for equalization and FEC interface
- SerDes characterization: eye diagram analysis, jitter decomposition, and BER floor measurement
- Co-design with PCB signal integrity team: channel analysis, loss budget, and pre-emphasis tuning
- Protocol compliance validation: PCIe CEM, USB compliance, Ethernet OIF CEI specifications
- FinFET-node SerDes implementation: layout-dependent effects, parasitic mitigation, power headroom
Tools & Technologies
The stack our SerDes Design engineers actually ship in.
Program context
112G Shipping. 224G in Development. Scarce Talent
SerDes is the circulatory system of modern semiconductor. Every AI accelerator, every 400G/800G Ethernet switch ASIC, and every high-performance SoC needs high-speed serial interconnect. And the data rate doubles roughly every three years. From 28G NRZ to 56G PAM4 to 112G PAM4 and now 224G, each generation requires analog circuits that push deeper into the noise floor, with tighter jitter budgets, narrower power headroom, and more sophisticated equalization algorithms. Engineers who have silicon-proven 112G PAM4 SerDes at 7nm or 5nm are among the most valuable individuals in semiconductor.
FAQ
Common Questions on SerDes Design Staffing
What makes SerDes design different from general analog design?+
SerDes sits at the intersection of analog circuits, mixed-signal design, and DSP algorithm development. A SerDes Rx path includes an analog front end (CTLE, DFE), clock and data recovery (CDR), and digital adaptation algorithms that tune equalization in real time based on channel conditions. A SerDes Tx path has driver circuits, pre-emphasis stages, and PLL jitter performance requirements that affect bit error rate at the system level. Engineers need to understand the full link. From transistor sizing through system-level BER floor. And they need lab skills to debug silicon.
What does the transition from NRZ to PAM4 mean for SerDes engineers?+
NRZ uses two voltage levels to encode one bit per symbol. PAM4 uses four levels to encode two bits per symbol. Doubling throughput at the same baud rate. The tradeoff: PAM4 has 1/3 the eye height of NRZ, making it dramatically more sensitive to noise, jitter, and inter-symbol interference. PAM4 at 56G or 112G requires more aggressive equalization, DSP adaptation algorithms, and analog front ends with a lower noise floor than NRZ required. Engineers who have only designed NRZ SerDes have not solved the PAM4 problem.
Can Game 7 place SerDes characterization and bring-up engineers specifically?+
Yes. SerDes characterization is a distinct phase and a distinct skill set from design. Characterization engineers bring up silicon in the lab, measure eye diagrams, decompose jitter (random, deterministic, periodic), map BER floors, tune equalization settings, and correlate results to pre-silicon simulations. They need strong lab skills. High-bandwidth oscilloscopes, BER testers, vector network analyzers. And the statistical fluency to interpret measurements correctly.
How does channel analysis factor into SerDes design?+
SerDes does not design in isolation. The link budget. Insertion loss, return loss, crosstalk, via discontinuities, connector transitions. Is determined by the PCB and package channel. A SerDes design optimized for a flat channel will fail in a real backplane. Experienced SerDes engineers work with the SI team to characterize the channel (using VNA or S-parameter simulation), define the equalization requirements, and verify that the analog front end has sufficient gain and dynamic range for the worst-case channel. Co-design between SerDes and PCB SI is essential at 112G PAM4 and beyond.
Related disciplines
Cross-Links Across the Team
Custom Analog IC and Mixed-Signal Designers
Broader analog IC design for PLL, ADC, and power management.
PCB Layout Engineers →High-Speed PCB Layout Engineers: DDR5, SerDes, RF
Channel design and loss budget partners for SerDes link teams.
Physical Design Engineers →Floorplan, P&R, STA, and Signoff Engineers for Advanced Process Nodes
PD engineers who close layout-dependent parasitics on SerDes PHYs.
Let's talk
Need a SerDes Design Engineer?
Tell us the program. We'll send a shortlist of 2-4 qualified engineers within days.