UCle 3.0, HBM4 and IEEE 1838 moved the hard part off the die. Three packaging and interconnect seats most chiplet programs never wrote a req for.
You've probably sat in this meeting: a stacked part is failing at final test, and everybody in the room is "right". Your logic owner has clean data, timing closed, the board team measured the channel at the connector and found nothing wrong with it; yet the yield number hasn't moved.
The problem is living in the substrate between two dies, and on most programs that boundary doesn't have an owner, no objective attached to it, and nobody whose review it shows up in.
What the Specs Just Did to Your Org Chart
UCle 3.0, released August 5 in 2025, doubled the die-to-die data rate to 38 and 64 GT/s for UCle-S and UCle-A, added runtime recalibration, and stretched sideband reach to 100 mm. The release before it, UCle 2.0 in August 2024, brought in a manageability system architecture and 3D packaging support. The interconnect engineers we work with read that pair of releases as a description of a link that now has to be calibrated, monitored and debugged in service, which is a different job from designing one.
Memory went the same direction. JEDEC published HBM4 as JESD270-4 on April 16, 2025: a 2048-bit interface at up to 8 Gb/s per pin, up to 2 TB/s per stack, and 32 independent channels with two pseudo-channels each, double the channel count of HBM3. Syack heights run to 16-high. Every one of those numbers eventually lands on your bump map, and somebody has to own it.
Test caught up too. IEEE 1838-209 defines a test access architecture for three-dimensional stacked ICs, the formal answer to a question chiplet programs ask late:
How do you prove a die is good before committing it to a stack you cannot rework?
Three Seats You Are Probably Writing as One
The advanced packaging engineer owns substrate stackup, bump maps, interposer design and the integration calls inside CoWoS, EMIB, Foveros or SoIC flows. The enginers in this seat tell us the decisions that hurt are the early ones, because a bump pitch chosen in month two shows up as a power delivery constraint during month nine. Most teams discover they needed this person when a foundry or OSAT asks a question nobody can answer without a week of study.
The package SI/PI engineer. The power and signal integrity engineers we work with describe HBM4 at 8 Gb/s across 2048 signals, alongside UCle-A at 64 GT/s, as the point where their job stopped ending at the package edge. The way they put it, your loss budget now closes across a boundary that used to be two teams' separate problem, so the channel becomes one continuous thing from die pad to board, analyzed in Ansys HFSS, Slwave or Cadence Sigrity and then proven on the bench.
The DFT architect who owns 3D test access. Different from the DFT engineer inserting scan on a single die, this one plans known-good-die screening, per-die test before stacking, and access into a stacked part against IEEE 1838. The DFT architects we place are blunt about the timing: test access into a 3D stack is set by die partitioning, so bringing this person in afterwards buys you workarounds rather architecture.
Your Req Is Precise About the Wrong Thing
"Senior Physical Design Engineer, 3m" is exact about the node but silent about the package, so the shortlist arrives full of engineers who have never opened a substrate design. The fix is unglamorous, yet effective: name three things you are currently leaving out.
- The package technology, specifically. 2.5D on a CoWoS-class interposer reads very differently from fan-out.
- The memory you're integrating, this program and next. HBM3E today, HBM4 tomorrow is a real sentence to an engineer who's already done it.
- The interconnect, by name. UCle die-to-die tells a candidate more than any seniority label will.
Skip the Tool List, Hand Them a Failure
Put a scenario in front of your candidate instead. A 2.5D part passes at wafer sort, fails intermittently at final test after assembly, and the failures cluser on one HBM stack. What do you look at, in what order, and what do you want from the OSAT?
The answers separate fast. Someone who has lived it starts narrowing between assembly-induced damage, a marginal channel and a test-access gap and wants to know who owns the known-good-die screen.
One follow-up that is worth your time: who did you work with at the OSAT, and what did that relationship actually involve? Advanced packaging is a program you run with an outside partner, and the people who have run one talk about it in names and review cycles rather than tool lists.
Small Pool, Unforgiving Calendar
From where we sit in this market, the engineers who have taken a 2.5D program with HBM integration from partitioning through bring-up number in the hundreds, not thousands, and a good share of them sit inside a handful of companies. That is a narrow pool to hire against on a schedule set by a foundry capacity slot.
Search speed is the part you control. Two in three of the engineers we put in front of a hiring manager receive an offer, roughly three times the industry norm, which is what a shortlist build on package technology instead of a job title looks like. We submit the first candidate inside 24 hours of a job being created, and our mediant to an offer extended is only 19 days.
None of it makes the physics easier. It does get the seam an owner before the bump map locks, which is the whole difference. If you are staffing a chiplet or advanced packaging program, tell us what you're building and which seam is worrying you, and we'll tell you what the pool actually looks like for it.
FAQ
Frequently Asked Questions
What roles does a 2.5D or chiplet program actually need?
Beyond the die-level teams, three seats keep getting missed. An advanced packaging engineer for substrate stackup, bump maps and interposer integration. A package SI/PI engineer who owns the channel from die pad through substrate and interposer to the board. And a DFT architect who plans known-good-die screening and test access into a stacked part against IEEE 1838. Most reqs name none of the three, which is why shortlists arrive full of die-side engineers.
What is the difference between a package engineer and a package SI/PI engineer?
A package engineer designs the structure: substrate stackup, bump map, layer count, and the integration decisions insude a CoWoS, EMIB, Foveros, or SoIC flow. A package SI/PI engineer analyzes what signals and power delivery do across that structure, in tools like Ansys HFSS, Slwave or Cadence Sigrity, then proves it on a bench. The engineers we place say the two roles share vocabulary and rarely share a person.
When should you hire and advance packaging engineer?
Before the bump map and floorplan lock. The engineers in this seat tell us the decisions that hurt are often the early ones, because a bump pitch chosen in month two turns into a power delivery constraint in month nine. Test access is even less forgiving, since it's set by die partitioning: a DFT architect brought in afterwards ends up designing workarounds rather than an architecture.
Why do physical design recs fail to find the right packaging engineers?
Because a req that specifies the node and omits the package reads as a die-side role. "Senior Physical Design Engineer, 3nm" is exact about process and silent about substrate, so it attracts engineers who have never opened a package design. Naming the package technology, the memory generation and the interconnect, for instance 2.5D on a CoWoS-class interposer with HBM4 and UCle die-to-die, filters much harder than any seniority label.
Written by
Game 7 Staff