ASIC Design Engineer

Location: Remote (U.S. only)

Headcount: 1

Contract: 12 months; Start: 2026-11-16

If Resume Is on the Fence: 1. HM first screen, 2. Panel interview with leads (4 people on Teams call);

Why Hiring

• Part of a workforce plan to add about 10 people and convert as needed to support upcoming tape-out milestones.

End Product

• Ultraflex 2 platform and Magnum platform supporting new instruments and ASICs simultaneously.

Tech / Domain Environment

• Verilog
• LP DDR 5, PCIe Gen 5, NVMe, UFX flash interfaces

Job Duties

• Write specifications from high-level architecture specs with chip architects
• Implement designs using RTL on a blank piece of paper
• Ensure designs work in context of higher-level design
• Document upcoming work before implementation
• write specs from high-level architects' specs and then design it
• not just pure coding

Must Haves

• Verilog coding
• needs someone who really understands the block they're designing
• 10+ years of experience doing the microarchitecture, design and implementation of blocks
• someone who is good at documenting what they're going to do before they do it
• Experience making sure it works in the context of higher-level design and then implementing the design with RTL

Nice to Haves

• LP DDR 5
• PCIe Gen 5
• Flash memory: NVMe or UFX flash interfaces