RTL Design Engineer

Headcount: 4

(Will consider other locations but California is preferred)

Contract: October 2026 - May 2027 (potential extension past May 2027); Start: Immediate

Why Hiring

• Workforce expansion to support core engineering initiatives with heavy focus on RTL design and FlexNoC configuration.

End Product

• High-performance semiconductor chips and networking components utilizing advanced Network-on-Chip (NoC) architectures.

Tech / Domain Environment

• RTL design
• FlexNoC

Job Duties

• This is SoC Interconnect / NoC RTL Integration Engineer role, not a traditional RTL designer designing individual blocks
• Configure FlexNoC architectures, defining initiators, targets, address maps, clock domains, and QoS parameters.
• Perform RTL design tasks and collaborate with cross-functional engineering teams to resolve integration issues.

Must Haves

• Demonstrated project experience configuring FlexNoC, including hands-on work with initiators, targets, address maps, clock domains, and QoS settings.
• 3 recent years using FlexNoc

Nice to Haves

• Prior background working within acquired semiconductor sectors or similar high-scale enterprise chip design environments.

Security / Clearance

• None specified