Section
About the Role
Title: Senior FPGA Architect, Compute Test
Headcount: 1
Location: North Reading, MA; Hybrid; 3 days/week when needed for lab bring-up
Contract: 6 months; Start: 2026-10-01
Interview Process: 1-2 video or phone calls (hour-long); Feedback SLA: Ad-hoc
Why Hiring:
- Team growth to support new FPGA compute projects starting in Q4/Q1.
End Product:
- Compute Test North Reading FPGA platform supporting new compute test projects and board architectures.
Tech/Domain Environment:
- Xilinx or Intel Altera FPGA tool chains
- High-speed interfaces, high-speed memories, SerDes transceivers, 10G/100G Ethernet, PCI Express, DDR memories
- Low-speed serial and parallel interfaces (I2C, SPI, USB)
Job Duties:
- Own entire FPGA architecture and design trade-offs at board level
- Write RTL code and contribute directly to design implementation
- Collaborate with PCB and software engineering teams
- Scope project requirements and delegate tasks
- Perform lab bring-up when hardware arrives
Must Haves:
- FPGA architecture and design experience (8+ years required, 12+ preferred)
- Xilinx or Intel Altera FPGA tool chains
- High-speed interfaces and high-speed memories
- SerDes transceivers, 10G/100G Ethernet, PCI Express, DDR memories
- Low-speed serial and parallel interfaces (I2C, SPI, USB)
Disqualifiers:
- Multiple 1-year or shorter stints (job hopping red flag)
- Candidates fresh out of school applying for senior architect roles
Security/Clearance:
- Not specified