Section
About the Role
Title: RTL Design / Design Verification Engineer
Headcount: 2 RTL and 1 DV openings
Location: Hybrid/Remote with customer site travel to Bay Area or India; ideal preference for on-site presence or travel ability
Contract: 1-year contract duration preferred on 2-year project with potential extension or full-time conversion; Start: October 1st preferred
Interview Process: Initial filter and interview with Arnauv or alternative team members, keeping process under two calls; Feedback SLA: Weekly
Why Hiring:
- High priority project to support semiconductor companies with design and verification services
End Product:
- Semiconductor design blocks and verification services prior to customer tape-out
Tech/Domain Environment:
- Custom-built AI workflow tools and formal verification engines
- PCIe, UVM environment for ARM wrapper, ML subsystem
- Jasper Gold and internal formal verification tools
Job Duties:
- Work directly in production on customer-facing design blocks including RTL, DB jobs, and CPU subsystem integration
- Work across 20 smaller blocks over two years using custom-built AI workflow tools
- Focus on design ownership of smaller IPs rather than critical modules
- Perform verification prior to customer tape-out with full individual ownership
Must Haves:
- 10+ years of experience with production-level work at high-level companies like Intel, NVIDIA, Broadcom, or Marvell
- Experience with PCIe and UVM environments for ARM wrappers
- Experience with ML subsystems finding real bugs
- Proven formal verification experience
Nice to Haves:
- Startup experience understanding startup life and demands
Disqualifiers:
- Candidates who have only been part of a team without full design ownership
- Candidates who have not stayed up to date with recent developments in the field
Security/Clearance:
- [Not captured]