Design Verification Engineer

Chips & Silicon · Palo Alto Office (remote considered) · Contract

About Us

We are developing world models, and agents to learn, evaluate, plan, experiment, and interact with the physical world. We are starting out with understanding and building hardware; electronics systems and semiconductors where AI can design and create beyond human cognitive limits.

About the Team

Backed by Silicon Valley's top investors, Stanford University, and CEOs/Presidents of Google, AMD, Broadcom, Marvell, etc. We are a team of previous Stanford professors, SAIL researchers, Olympiad medalists (IPhO, IOI, etc.), CTOs of Synopsys & GlobalFoundries, Head of Sales & CRO of Cadence, former US Secretary of Defense, National Security Advisor, and Senior Foreign-Policy Advisor to four US presidents.

About this Role

We are building next- generation tools for silicon design by combining deep verification expertise with modern AI systems. You will be part of a silicon design team that delivers RTL and verification for leading semiconductor companies on schedules conventional teams can't match, by pairing experienced engineers with AI-driven design and verification tooling. As a Design Verification Engineer, you will own verification for blocks and subsystems on real customer SoC programs, from testbench architecture through coverage closure and signoff, and you'll use AI throughout your workflow to get there faster. If you want to build tools that scale with the new era of complexity in hardware, this role offers high ownership and direct impact on real-world chip development.

What You'll Do

• Own the verification plan, testbench architecture, and signoff for SoC blocks and subsystems, including interconnects, switches, and CPU clusters.

• Build and maintain SystemVerilog/UVM environments, sequences, scoreboards, and checkers.

• Verify high-speed interfaces and subsystems such as PCIe, Ethernet, and CPU integration.

• Run regressions, track coverage, triage failures, and root-cause bugs across RTL, testbench, and spec.

• Set up verification flows from scratch on new programs and get them running quickly.

• Use AI-assisted verification tools to accelerate test generation, debug, and coverage closure, and help shape how those tools evolve.

• Work directly with customer verification and design teams, on-site when the program requires it.

• Find ways to optimize the verification process and try new methodologies where they cut schedule.

What Makes This Role Unique

• Work on production silicon at top semiconductor companies, with AI tooling most DV teams don't have yet.

• High ownership from day one, with direct customer interaction and real accountability for signoff.

• Help define how a modern, AI-native verification team operates.

• Fast-moving environment built for engineers who take initiative rather than wait for direction.

Qualifications

• 6+ years of hands-on design verification experience with multiple production tapeouts, ideally at an established semiconductor company.

• Strong SystemVerilog and UVM skills with proven debug depth.

• Direct experience verifying Arm CPU clusters, interconnects or switches, PCIe, Ethernet, or CPU/subsystem integration.

• Comfortable using AI tools as part of your daily workflow, and eager to push them further.

• Able to ramp onto a new design and contribute within days, without hand-holding.

• Fast-moving and results-driven, with a track record of closing verification under tight schedules.

• Comfortable interacting directly with customer engineering teams.

Bonus Skills

• Experience with formal verification (JasperGold, VC Formal, or similar) and SVA.

• Experience with VIP for AMBA, PCIe, or Ethernet.

• Familiarity with emulation or hardware-accelerated simulation.

• Previous consulting, contract, or forward-deployed engineering experience.