Circuit Designer / Post-Silicon Validation Engineer (TEST

Title: Circuit Designer / Post-Silicon Validation Engineer

Headcount: 2

Location: Remote US (Circuit Design) and Raleigh, NC (Post-Silicon Validation) / Hybrid/Remote

Contract: April 2026 through October 2026; Start: 2026-04-01

Interview Process: Resume review followed by 30 to 45 minute technical interview with technical lead; Feedback SLA: Not captured

Why Hiring:

- New project requiring additional manpower for derivative SRAM IP design and bench post-silicon validation environment.

End Product:

- SRAM derivative IP design and bench post-silicon validation for AI cloud and satellite SOC programs.

Tech/Domain Environment:

- Python programming

- Oscilloscopes, voltage generators, thermal chambers

- Nanotime timing characterization

- SPICE, HSPICE

Job Duties (6-10 bullets):

- Design derivative SRAM IP

- Generate timing Liberty files

- Perform EMIR functional verification

- Analyze circuit margins

- Develop Python-based bench software environments

- Perform data collection and lab debug

Must Haves (hard gates; 6-12 bullets, all testable/quantified):

- SRAM experience

- Timing Liberty generation

- EMIR functional verification

- FinFET experience

- Register file experience

- Python programming

- Bench equipment operation (oscilloscopes, voltage generators, thermal chambers)

- Nanotime

Nice to Haves (5-10 bullets):

- Nanotime timing characterization experience

Disqualifiers (3-6 bullets):

- Not captured

Security/Clearance:

- Not captured