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About the Role
Title: PCB Layout Engineer — Contract
Headcount: 2+
Location: Costa Mesa, CA — on-site first ~month (performance evaluation), then hybrid/remote if performing. Full remote from day one is not the default.
Start: ASAP
Interview process: ~30–45 min technical with hiring manager
Security / clearance: Eligible for U.S. security clearance
Why hiring:
Resolve a current PCB layout bottleneck with production Altium layout contractors who can join quickly and ship mixed-signal digital boards without a long ramp.
End product:
Release manufacturable PCB layouts for aerospace/defense mixed-signal boards with digital and analog/power context, handed from EE Design schematics.
Tech / domain environment:
Altium Designer in recent, production layout use.
Typical boards are ~8–10 layers; denser HDI and >10-layer experience is preferred.
Mixed-signal boards with real high-speed digital and controlled-impedance routing, including USB, Ethernet, or PCIe-class interfaces as applicable.
Fast, directed team where contractors complete layouts quickly.
Job duties:
Own PCB layout in Altium from schematic packages through release-quality outputs.
Apply stack-up, placement, routing, plane, and constraint practices appropriate to each design.
Route controlled-impedance and high-speed digital interfaces to the design rules.
Apply fabrication and assembly limitations and best practices; support DFM/DFA discussions with vendors as needed.
Use and maintain ECAD library practices as required by the team.
Take direction from EE Design and the layout lead; collaborate to finish boards on schedule.
Work on-site for the initial ramp-up period; move hybrid/remote only if output quality and pace hold.
Must haves:
3+ years of PCB layout in production.
3+ years of recent, hands-on Altium layout in current/production use.
Read and interpret schematics and apply layout best practices per design.
Solid understanding of PCB fabrication and assembly processes, limitations, design rules, and best practice.
Experience with ECAD libraries and library management.
Familiarity with basic SI and PI rules and how they affect layout.
Experience with high-speed digital interfaces and controlled-impedance routing, including USB, PCIe, or Ethernet.
Work in a team, take direction, and complete designs quickly.
Work on-site in Costa Mesa for the initial ~1-month ramp-up
Eligible for U.S. security clearance.
Current/production use of Altium; decade-old Altium only does not count.
Demonstrate real Altium layout fluency through a hands-on layout exercise.
Ability to work on-site in Costa Mesa for the initial evaluation period, then hybrid/remote only if performing.
Nice to haves:
CID, CID++, and/or PCEA-CPCD certification.
MIL-STD and IPC standards experience.
High-density routing, including BGA fanout, stack-ups >10 layers, and HDI.
Deeper high-speed routing experience with PCIe, DDR, or similar interfaces.
PDN and signal integrity analyzer exposure.
Vendor DFM/DFA collaboration.
BS EE or similar.
Light schematic literacy beyond read-only and light bring-up support; not a substitute for layout depth.
Comfort as the layout owner on mixed-signal digital boards with impedance-controlled nets.
Thrives in a fast-paced environment.
Disqualifiers:
Fewer than 3 years of Altium experience or no recent production Altium use.
Cannot demonstrate real Altium layout fluency in basic hands-on layout tasks.
Mixed-signal résumé with no controlled-impedance or high-speed digital routing.
Pure schematic/EE Design profile with weak layout depth.
Harness/Capital/NX-only profile.
Cannot work on-site for the initial evaluation period.
Not eligible for U.S. security clearance.
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