Design Verification Engineers
Full-custom and standard-cell physical design for sub-5nm ASIC and SoC programs. Senior and Principal physical design engineers with Synopsys and Cadence flow experience and tape-out signoff credentials.
WHAT THEY DO
Physical implementation from floorplan through tape-out signoff.
Senior and Principal physical design engineers at Game 7 have closed timing, power, and physical verification on complex SoC blocks at advanced nodes - they haven't just run the tools.
They make floorplan architecture decisions, set PD methodology, manage multi-corner STA closure across PVT, and own the GDS delivery. At 5nm and below, they've dealt with multi-patterning constraints, FinFET layout rules, increased hold sensitivity, and the complexity of delivering clean physical verification sign-off to the foundry.
ENGINEERING Checklist
- Chip and block floorplanning with power distribution network (PDN) and I/O planning
- Place and route for high-performance, low-power, and area-constrained designs
- Static timing analysis (STA) and multi-corner timing closure across PVT corners
- IR drop and electromigration (EM) analysis and closure using RedHawk or Voltus
- Physical verification (DRC, LVS, ERC) using Calibre and Assura
- Clock tree synthesis (CTS) for high-fanout, skew-sensitive designs
- Multi-patterning and advanced node layout constraint management (FinFET, GAAFET)
- Tape-out signoff and GDSII delivery
Tools & Technologies
Cadence Innovus · Synopsys ICC2 · PrimeTime · Calibre · StarRC · Virtuoso · Redhawk · Voltus