Design Verification Engineers
Block-to-chip-level design verification using UVM, SystemVerilog, and formal methods. Mid, Senior, and Principal DV engineers who have achieved functional coverage closure on complex SoC programs.
WHAT THEY DO
Verification closure, not just testbench construction.
Principal DV engineers at Game 7 have owned verification plans and driven coverage closure on complex subsystems; not just inherited a testbench and run regression.
They write UVM testbench architecture from scratch, define coverage models that actually catch bugs, and drive sign-off. They've debugged RTL bugs found by constrained-random after 50 million simulation cycles and written the assertions that prevent them from regressing. They know what 'functionally verified' means and what it takes to get there on a real program.
ENGINEERING Checklist
- UVM testbench architecture for block, subsystem, and chip-level verification
- Constrained-random stimulus generation and coverage model development
- Formal property verification and assertion-based verification (JasperGold, Questa Formal)
- Functional coverage closure and coverage-driven verification planning
- Simulation regression management, triage, and debug
- Protocol verification (AMBA AXI/AHB, PCIe, USB, DDR/LPDDR, MIPI CSI/DSI)
- Mixed-signal and analog/digital interface verification (VIP integration)
- Emulation and prototyping support (Cadence Palladium, Synopsys ZeBu)
Tools & Technologies
UVM · SystemVerilog · Synopsys VCS · Cadence Xcelium · JasperGold · Questa Formal · Verdi · Python