RISC-V job reqs are showing up. Not everywhere, not in every company… but enough that if you've been writing ARM-based firmware for the last several years, you're probably wondering how seriously to take it.

The honest answer: seriously, but not in the way the headlines suggest. RISC-V isn't replacing ARM. But it's also not a research project anymore. And if you wait for it to be dominant before learning anything about it, you'll fall behind.

Where RISC-V Is Actually Deployed Today

RISC-V International, the open standards body governing the ISA, now includes hundreds of member organizations across industry and academia. But membership data doesn't tell you where firmware engineers will encounter RISC-V targets.

Espressif's ESP32-C series runs RISC-V cores (RV32IMC) and is shipping at scale in IoT products worldwide. If you've done any embedded work in the connected device space, your clients may already be running hardware with RISC-V inside it.

SiFive, founded by the original RISC-V architects at UC Berkeley, has been shipping RISC-V IP cores for industrial and embedded Linux applications since 2016. Their HiFive development boards have been real RISC-V development hardware for engineers since.

In the datacenter and custom silicon space, a number of companies designing their own ASIC and SoC solutions have embedded RISC-V cores for control-plane firmware; the low-level management processor that sits alongside the main compute logic.

What's Actually Different for Firmware Engineers

Toolchain: RISC-V uses its own GCC cross-compiler (riscv32-unknown-elf-gcc for RV32). The workflow is structurally the same as arm-none-eabi-gcc. The ISA and peripheral model is the learning curve, not the build system.

Interrupt architecture: RISC-V uses PLIC (Platform-Level Interrupt Controller) for external interrupts and CLINT (Core-Local Interruptor) for timer and software interrupts; both different from ARM's NVIC. The RISC-V privileged architecture specification defines these in detail and is the primary reference document for this layer.

ISA modularity: RISC-V defines a base integer ISA (RV32I or RV64I) plus optional extensions: M (multiply), A (atomics), F/D (float), C (compressed). You compile against specific extension sets - the suffix rv32imac encodes what your target supports.

Peripheral standardization: ARM's CMSIS standard provides a consistent peripheral access layer across Cortex-M vendors. RISC-V has no equivalent. Peripheral register layouts are vendor-defined, and you're working from datasheets and vendor SDKs, similar to less-common ARM Cortex-M vendors.

What Your ARM Experience Is Actually Worth

More than you might think. The fundamentals - C programming, RTOS concepts, device driver patterns, interrupt hygiene, linker script structure, memory map management - are portable. If you know Zephyr RTOS (a Linux Foundation project with strong industry backing), you're already ahead. Zephyr has production-quality RISC-V support, including maintained board definitions for SiFive and Espressif ESP32-C targets.

If you know MISRA-C and functional safety processes, those are completely architecture-agnostic. Protocol experience (CAN, SPI, I2C, UART, Ethernet) transfers, and the protocol knowledge and driver architecture patterns don't change with the ISA.

What You'd Need to Learn

• The RISC-V base ISA: RV32I or RV64I instruction set, register file (x0–x31 with ABI names), calling convention, and the extension suffix system

• The privileged architecture: machine-mode CSRs (mstatus, mtvec, mcause, mepc, mie, mip), exception handling, and interrupt delegation

• Startup code and linker scripts: without CMSIS, you're writing from the vendor reference rather than adapting a standard template

• Debug tooling: Segger J-Link supports RISC-V, and OpenOCD has growing RISC-V support. The GDB interface is the same. Probe configuration takes some investment but it's not a large learning curve.

What This Means for Your Career Right Now

ARM experience is not at risk. The installed base is enormous, the toolchain is mature, and the ecosystem is entrenched. RISC-V is a broadening skill, not a replacement skill. Engineers who can work across both ecosystems are more valuable than those who can work in only one.

If you're a senior or principal embedded engineer with 8+ years of ARM experience, spending a weekend with a SiFive HiFive Unmatched or an ESP32-C3 dev board and a copy of the RISC-V privileged architecture spec is a low-cost investment with a real return. You'll cover most of the conceptual delta in a few focused hours.

RISC-V is real, it's shipping, and it's growing. Your ARM skills are valuable and won't be made obsolete by it. The engineers best positioned for the next decade of embedded work are the ones who can work fluently in both and the gap between your current knowledge and that point is smaller than the headlines make it sound.

If you'd like to discuss where you want to take your engineering career next, give one of our technical recruiters a call or fill out a quick form and we'll get back to you within a business day.

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